Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Synthesis of symmetric functions for path-delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-testable implementations of symmetric functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Testable design of digital summation threshold logic array for synthesis of symmetric functions
International Journal of Computers and Applications
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A new approach to synthesizing totally symmetric Boolean functions is resented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this module, a general symmetric function is then realized following a unate decomposition method. The cellular structure is simple and universal - it uses only 2-input, 2-output AND-OR cells, and admits a recursive construction. The design provides a significant reduction in hardware cost compared to other existing techniques.