Closing the gap between analog and digital testing

Authors:
K. Saab;N. B. Hamida;B. Kaminska
Affiliations:
Adaptive Networks Inc., Newton, MA;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
Cited 3

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A New Optimal Test Node Selection Method for Analog Circuit

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Abstract

This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing