Complexity of network synchronization
Journal of the ACM (JACM)
Conditional rewriting logic as a unified model of concurrency
Selected papers of the Second Workshop on Concurrency and compositionality
A logical theory of concurrent objects and its realization in the Maude language
Research directions in concurrent object-oriented programming
IEEE/ACM Transactions on Networking (TON)
Introduction to distributed algorithms
Introduction to distributed algorithms
Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
IEEE Transactions on Software Engineering
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Distributed Algorithms
Specification of real-time and hybrid systems in rewriting logic
Theoretical Computer Science - Rewriting logic and its applications
Equational rules for rewriting logic
Theoretical Computer Science - Rewriting logic and its applications
Membership algebra as a logical framework for equational specification
WADT '97 Selected papers from the 12th International Workshop on Recent Trends in Algebraic Development Techniques
Automatic Production of Globally Asynchronous Locally Synchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Bus Architectures for Safety-Critical Embedded Systems
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
An Overview of Formal Verification for the Time-Triggered Architecture
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
RTCAST: lightweight multicast for real-time process groups
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Semantic foundations for generalized rewrite theories
Theoretical Computer Science
Semantics and pragmatics of Real-Time Maude
Higher-Order and Symbolic Computation
IEEE Transactions on Software Engineering
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Implementing Synchronous Models on Loosely Time Triggered Architectures
IEEE Transactions on Computers
Verification of GALS Systems by Combining Synchronous Languages and Process Calculi
Proceedings of the 16th International SPIN Workshop on Model Checking Software
A Formal Architecture Pattern for Real-Time Distributed Systems
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Formalization and correctness of the PALS architectural pattern for distributed real-time systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Middleware design for physically-asynchronous logically-synchronous (PALS) systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
Taming distributed system complexity through formal patterns
Science of Computer Programming
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Many Distributed Real-Time Systems (DRTSs), such as integrated modular avionics systems and distributed control systems in motor vehicles, are made up of a collection of components communicating asynchronously among themselves and with their environment that must change their state and respond to environment inputs within hard real-time bounds. Such systems are often safety-critical and need to be certified; but their certification is currently hard due to their distributed nature. The Physically Asynchronous Logically Synchronous (PALS) architectural pattern can greatly reduce the design and verification complexities of achieving virtual synchrony in a DRTS. This work presents a formal specification of PALS as a formal model transformation that maps a synchronous design, together with a set of performance bounds of the underlying infrastructure, to a formal DRTS specification that is semantically equivalent to the synchronous design. This semantic equivalence is proved, showing that the formal verification of temporal logic properties of the DRTS in CTL^* can be reduced to their verification on the much simpler synchronous design. An avionics system case study is used to illustrate the usefulness of PALS for formal verification purposes.