Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Proceedings of the 15th international symposium on System Synthesis
Cell broadband engine processor: design and implementation
IBM Journal of Research and Development
Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms
IEEE Transactions on Parallel and Distributed Systems
Hierarchical Network-on-Chip for Embedded Many-Core Architectures
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Towards a parameterizable cycle-accurate ISS in ArchC
AICCSA '10 Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010
Light speed labeling: efficient connected component labeling on RISC architectures
Journal of Real-Time Image Processing
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
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The future high-end embedded systems applications are characterized by their computation-intensive workloads, their high-level of parallelism, their large data-set requirements, and their dynamism. Those applications require highly-efficient manycore architectures. In response to this problem, we designed an asymmetric homogeneous with dynamic allocator manycore architecture, called AHDAM chip. AHDAM chip exploits the parallelism on all its granularity levels. It implements multithreading techniques to increase the processors' utilization. We designed an easy programming model and reused an automatic compilation and application parallelization tool. To study its performance, we used the radio spectrum sensing application from the telecommunication domain. On a simulation framework, we evaluated sequential and parallel versions of the application on 2 platforms: single processor, and AHDAM chip with a variable number of processors. The results show that the application on the AHDAM chip has an execution time 574 times faster than on the single-processor system, while meeting the real-time deadline and occupying 51.92 mm2 at 40 nm technology.