Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants

Authors:
Miaoqing Huang;Vikram Narayana;Mohamed Bakhouya;Jaafar Gaber;Tarek El-Ghazawi
Affiliations:
University of Arkansas, Fayetteville;The George Washington University, Washington DC;Technical University of Belfort Montbeliard, Cedex;Technical University of Belfort Montbeliard, Cedex;The George Washington University, Washington DC
Venue:
IEEE Transactions on Computers
Year:
2012

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
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Proceedings of the International Conference on Computer-Aided Design

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Abstract

High-performance reconfigurable computing involves acceleration of significant portions of an application using reconfigurable hardware. Mapping application task graphs onto reconfigurable hardware is, therefore, of rising attention. In this work, we approach the mapping problem by incorporating multiple architectural variants for each hardware task; the variants reflect tradeoffs between the logic resources consumed and the task execution throughput. We propose a mapping approach based on the genetic algorithm, and show its effectiveness for random task graphs as well as an N-body simulation application, demonstrating improvements of up to 78.6 percent in the execution time compared with choosing a fixed implementation variant for all tasks. We then validate our methodology through experiments on real hardware, an SRC-6 reconfigurable computer.