Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Using model checking to generate tests from requirements specifications
ESEC/FSE-7 Proceedings of the 7th European software engineering conference held jointly with the 7th ACM SIGSOFT international symposium on Foundations of software engineering
Verification of a safety-critical railway interlocking system with real-time constraints
Science of Computer Programming
The Verus language: representing time efficiently with BDDs
Theoretical Computer Science - Special issue on real-time systems and concurrent and distributed software
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
The software model checker Blast: Applications to software engineering
International Journal on Software Tools for Technology Transfer (STTT)
European Train Control System: A Case Study in Formal Verification
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Journal of Automated Reasoning
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Predicate abstraction with adjustable-block encoding
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
CPACHECKER: a tool for configurable software verification
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
On the adoption of model checking in safety-related software industry
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
SATABS: SAT-Based predicate abstraction for ANSI-C
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Adoption of Model-Based Testing and Abstract Interpretation by a Railway Signalling Manufacturer
International Journal of Embedded and Real-Time Communication Systems
Defining and model checking abstractions of complex railway models using CSP||B
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
| Hi-index | 0.00 |
Formal verification and validation is a fundamental step for the certification of railways critical systems. Many railways safety standards (e.g. the CENELEC EN-50126, EN-50128 and EN-50129 standards implement the mandatory safety requirements of IEC-61508-7 standard for Functional and Safety) currently mandate the use of formal methods in the design to certify correctness. In this paper we describe an industrial application of formal methods for the verification and validation of "Logica di Sicurezza" (LDS), the safety logic of a railways ERTMS Level 2 system developed by Ansaldo-STS. LDS is a generic control software that needs to be instantiated on a railways network configuration. We developed a methodology for the verification and validation of a critical subset of LDS deployed on typical realistic railways network configurations. To show feasibility, effectiveness and scalability, we have experimented with several state of the art symbolic software model checking techniques and tools on different network configurations. From the experiments, we have successfully identified an effective strategy for the verification and validation of our case study. Moreover, the results of experiments show that formal verification and validation is feasible and effective, and also scales reasonably well with the size of the configuration. Given the results, Ansaldo-STS is currently integrating the methodology in its internal Development and Verification & Validation Flow.