Deterministic Computations on a PRAM with Static Processor and Memory Faults

  • Authors:
  • Bogdan S. Chlebus;Leszek Gasieniec;Andrzej Pelc

  • Affiliations:
  • Department of Computer Science and Engineering, University of Colorado at Denver, Campus Box 109, Denver, CO 80217-3364, USA;Department of Computer Science, University of Liverpool, Chadwick Building, Peach Street, Liverpool L69 7ZF, United Kingdom;Département d'informatique, Université du Québec en Outaouais, C.P. 1250, succ. B, Hull, Québec J8X 3X7, Canada

  • Venue:
  • Fundamenta Informaticae
  • Year:
  • 2003

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Abstract

We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. We develop a deterministic simulation of a fully operational PRAM on a similar faulty machine which has constant fractions of faults among processors and memory cells. The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and a constant fraction of m memory cells. The simulation is in two phases: it starts with preprocessing, which is followed by the simulation proper performed in a step-by-step fashion. Preprocessing is performed in time O(({m/n}+log n)log n). The slowdown of a step-by-step part of the simulation is O(log m).