Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

  • Authors:
  • Tuan-Vu Cao;Dag T. Wisland;Tor Sverre Lande;Farshad Moradi

  • Affiliations:
  • Nanoelectronics Group, University of Oslo, Oslo, Norway;Nanoelectronics Group, University of Oslo, Oslo, Norway;Nanoelectronics Group, University of Oslo, Oslo, Norway;Nanoelectronics Group, University of Oslo, Oslo, Norway

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2012

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Abstract

The voltage-controlled oscillator (VCO) in frequency-based $$\Updelta\Upsigma$$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving 驴125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670 μW at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $$\Updelta\Upsigma$$ modulator.