Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits
Design of a wideband low-power continuous-time ΣΔ modulator in 90 nm CMOS technology
Analog Integrated Circuits and Signal Processing
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma---delta (ΣΔ) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8 dB and dynamic range of 76.5 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling rate.