A Parallel infrastructure on dynamic EPIC SMT and its speculation optimization

Authors:
Qingying Deng;Minxuan Zhang;Jiang Jiang
Affiliations:
PDL, College Of Computer, National University Of Defense, Technology, Changsha, Hunan, P.R. China;PDL, College Of Computer, National University Of Defense, Technology, Changsha, Hunan, P.R. China;PDL, College Of Computer, National University Of Defense, Technology, Changsha, Hunan, P.R. China
Venue:
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Year:
2007

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Abstract

SMT(simultaneous multithreading) processors execute instructions from different threads in the same cycle, which has the unique ability to exploit ILP(instruction-level parallelism) and TLP(thread-level parallelism) simultaneously. EPIC(explicitly parallel instruction computing) emphasizes importance of the synergy between compiler and hardware. Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. Control and data speculations are effective ways to improve instruction level parallelism. In this paper, we present our efforts to design and implement a parallel environment, which includes an optimizing, portable parallel compiler OpenUH and SMT architecture EDSMT based on IA-64. Meanwhile, its speculation is also reexamined.