Microprocessing and Microprogramming
VLSI array algorithms and architectures for RSA modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
A Timing Attack against RSA with the Chinese Remainder Theorem
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Highly Regular Right-to-Left Algorithms for Scalar Multiplication
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Mycrypt'05 Proceedings of the 1st international conference on Progress in Cryptology in Malaysia
Algorithm engineering for public key algorithms
IEEE Journal on Selected Areas in Communications
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We (re-) introduce the Reduce-By-Feedback scheme given by Vielhaber (1987), Benaloh and Dai (1995), and Jeong and Burleson (1997). We show, how to break RSA, when implemented with the standard version of Reduce-by-Feedback or Montgomery multiplication, by Differential Power Analysis. We then modify Reduce-by-Feedback to avoid this attack. The modification is not possible for Montgomery multiplication. We show that both the original and the modified Reduce-by-Feedback algorithm resist timing attacks. Furthermore, some VLSI-specific implementation details (delayed carry adder, re-use of MUX tree and logic) are provided.