Architecture and implementation of MEMORY CHANNEL 2
Digital Technical Journal
Communication Optimizations for Fine-Grained UPC Applications
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Reconfigurable hybrid interconnection for static and dynamic scientific applications
Proceedings of the 4th international conference on Computing frontiers
WAINA '11 Proceedings of the 2011 IEEE Workshops of International Conference on Advanced Information Networking and Applications
INAM - a scalable infiniband network analysis and monitoring tool
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
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The latency of network switching is of particular importance for fine-grained communication processes such as memory access. We propose a specialized network switch that reduces communication latency because many scientific computing applications have specific access patterns. In this paper, we describe the basic concept and design of our reconfigurable shared memory network. Our evaluation results show that there is no significant difference between the port-to-port latency of our network switch and that of an 8-port InfiniBand network switch. Furthermore, the hardware size of the routing stack in the network switch does not increase with the number of nodes.