An architecture for a high performance rendering engine

Authors:
Hans-Josef Ackermann;Christoph Hornung
Affiliations:
-;-
Venue:
EGGH'91 Proceedings of the Sixth Eurographics conference on Advances in Computer Graphics Hardware: rendering, visualization and rasterization hardware
Year:
1991

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Abstract

We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.