Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
A Scalable FPGA-based Multiprocessor
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Maxwell - a 64 FPGA Supercomputer
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Axel: a heterogeneous cluster with FPGAs and GPUs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support unstructured (e.g., logs) and semi-structured (e.g., large graph, XML) data sets. To explore the suitability of FPGAs for these computations, we are constructing an FPGA-based system with a memory capacity of 512 GB from a collection of 32 Virtex-5 FPGAs spread across 8 enclosures. This poster describes the system's interconnect that combines inter-enclosure high-speed serial links and wide, single-ended intra-enclosure on-board traces with a network topology that optimizes for latency and bandwidth for small packets. The network uses a multi-level radix-12 router optimized for the asymmetry between the inter- and intra-enclosure links. The system has a peak theoretical bisection bandwidth of 247.2 Gb/s and a total switching capacity of 2.13 Tb/s. Under random traffic, the network sustains an aggregate throughput of 354.3 Gb/s. The channel transceivers and router consume 22% of the FPGAs' Block RAMs and 33% of their FPGA Slices.