PTL: PRAM translation layer

Authors:
Gyu Sang Choi;Byung-Won On;Kwonhue Choi;Sungwon Yi
Affiliations:
Department of Information and Communication Engineering, Yeungnam University, 214-1, Dae-dong, Gyeongsan, Gyeongsangbuk 712-749, Republic of Korea;Advanced Institutes of Convergence Technology (AICT), Seoul National University, 864-1 lui-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do 443-270, Republic of Korea;Department of Information and Communication Engineering, Yeungnam University, 214-1, Dae-dong, Gyeongsan, Gyeongsangbuk 712-749, Republic of Korea;Electronics and Telecommunications Research Institute, 138 Gajeongno, Yuseong-gu, Daejeon 305-700, Republic of Korea
Venue:
Microprocessors & Microsystems
Year:
2013

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Abstract

In this paper, we attempt to replace NAND Flash memory with PRAM, while PRAM initially targets replacing NOR Flash memory. To achieve it, we need to handle wear-leveling issue of PRAM since the maximum number of writes in PRAM is only 10^6. Thus, we have proposed PRAM Translation Layer (PTL) to resolve endurance problem for a PRAM-based storage system. We modified FlashSim to support both PRAM and NAND Flash memory and measured the performance by using real workloads from PC and server. In our experiment, PRAM shows up to 300% performance improvement compared to NAND Flash memory. Moreover, our results revealed that the PRAM's endurance is improved up to 25% compared to NAND Flash memory due to no erase operation. All these results suggest that PRAM is a viable candidate to replace NAND Flash memory.