An FPGA acceleration for the kd-tree search in photon mapping

Authors:
Takuya Kuhara;Takaaki Miyajima;Masato Yoshimi;Hideharu Amano
Affiliations:
Graduate School of Science and Technology, Keio University, Yokohama-shi, Kanagawa-ken, Japan;Graduate School of Science and Technology, Keio University, Yokohama-shi, Kanagawa-ken, Japan;Graduate School of Informatics Systems, The University of Electro-Communications, Chofu, Tokyo, Japan;Graduate School of Science and Technology, Keio University, Yokohama-shi, Kanagawa-ken, Japan
Venue:
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Year:
2013

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Abstract

Photon mapping is a kind of rendering techniques which enables depicting complicated light concentrations for 3D graphics. Searching kd-tree of photons with k-near neighbor search (k-NN) requires a large amount of computations. As k-NN search includes high degree of parallelism, the operation can be accelerated by GPU and recent multi-core microprocessors. However, memory access bottleneck will limit their computation speed. Here, as an alternative approach, an FPGA implementation of k-NN search operation in kd-tree is proposed. In the proposed design, we maximized the effective throughput of the block RAM by connecting multiple Query Modules to both ports of RAM. Furthermore, an implementation of the discovery process of the max distance which is not depending on the number of Estimate-Photons is proposed. Through the implementation on Spartan6, Virtex6 and Virtex7, it appears that 26 fundamental modules can be mounted on Virtex7. As a result, the proposed module achieved the throughput of approximately 282 times as that of software execution at maximum.