ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Virtual channels vs. multiple physical networks: a comparative analysis
Proceedings of the 47th Design Automation Conference
A hybrid packet-circuit switched on-chip network based on SDM
Proceedings of the Conference on Design, Automation and Test in Europe
Power and Performance Tabu Search Based Multicore Network-on-Chip Design
ICPPW '10 Proceedings of the 2010 39th International Conference on Parallel Processing Workshops
Low Power Networks-on-Chip
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip
Proceedings of the 4th International Workshop on Network on Chip Architectures
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The Networks-on-Chip paradigm has been seen as an interconnect architecture solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip. Moreover, the execution of different applications requires flexible and transparent interconnection solutions, and this feature is best provided by a selfadaptable system. In this paper we propose HASIN, an architecture that explores the suitable switching architecture according to the traffic in each region of the system, in a hierarchical manner. The proposed interconnection allows adapting the network at runtime using three switching possibilities to reconfigure itself according to the floorplan information. HASIN allows increasing the throughput up to 77% and reducing the power consumption up to 76% when compared to a packet-switched mesh network-on-chip.