Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Floorplanning and topology generation for application-specific network-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hierarchical and multiple switching NoC with floorplan based adaptability
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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Application-specific network-centric architectures (such as Networks on-Chip, NoCs) have recently become an effective solution to support high bandwidth communication in Multiprocessor Systems-on-Chip (MPSoCs). Moreover, the introduction of the hierarchy concept in the NoC design benefits from the main locality nature of the communication in MPSoC architectures. This paper presents a methodology to design Application Specific Hierarchical NoC (ASHiNoC) architectures considering foorplanning information. The presented approach targets heterogeneous clustered architectures where the intra-cluster communication is managed by a low-latency circuit-switched crossbar, while the inter-cluster communications are managed by a high-bandwidth packet-based NoC, allowing regulars topologies. The proposed design flow faces the problem by starting from the cluster selection down-to the foorplanning-aware estimation of the interconnect performances in terms of latency, power, area within each cluster and for the backbone NoC. Experimental results show that the AHiNoC architecture is able to guarantee an interconnection power and latency reduction of 49% and 33% respectively, at a cost of an area increment of 78% with respect to a flat topology version.