Fine-grained network time synchronization using reference broadcasts
ACM SIGOPS Operating Systems Review - OSDI '02: Proceedings of the 5th symposium on Operating systems design and implementation
Adaptive clock synchronization in sensor networks
Proceedings of the 3rd international symposium on Information processing in sensor networks
The flooding time synchronization protocol
SenSys '04 Proceedings of the 2nd international conference on Embedded networked sensor systems
Secure Time Synchronization in Sensor Networks
ACM Transactions on Information and System Security (TISSEC)
FPGA Based High Date Rate Radio Interfaces for Aerospace Wireless Sensor Systems
ICONS '09 Proceedings of the 2009 Fourth International Conference on Systems
On minimum variance unbiased estimation of clock offset in a two-way message exchange mechanism
IEEE Transactions on Information Theory
Cross-Layered Synchronization Protocol for Wireless Sensor Networks
ICN '10 Proceedings of the 2010 Ninth International Conference on Networks
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IEEE Communications Magazine
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In this paper, we present a Wireless Sensor node implementation which aims at solving two major issues in Wireless Sensor Networks. This solution provides nanosecond-scale synchronization between nodes and high data-rate transmission thanks to cross-layer design and the time-domain properties of UltraWide Band (UWB) modulation schemes. The high data rate is achieved through a specific implementation of a IR-UWB physical layer. Specific algorithms are also implanted into the MAC and physical layers and form a cross-layered synchronization protocol for deterministic Wireless Sensor Networks named WiDeCS (Wireless Deterministic Clock Synchronization). This protocol propagates master time reference to nodes of a cluster tree network. WiDeCS Cross layered scheme is possible thanks to flag signals rising in the physical layer. These signals, owing to the UWB time domain properties, capture precise timestamps of transmission and reception. Hardware level simulations show a clock synchronization precision of 2ns with a 2GHz bandwidth signal, and an ASIC demonstrator shows 374ps synchronization precision and 677ps of standard deviation with the same bandwidth. In this paper, the physical layer implementation is detailed, and the cross-layered WiDeCS scheme is demonstrated.