Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Software-Pipelining on Multi-Core Architectures
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Speculative Decoupled Software Pipelining
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
SPADE: the system s declarative stream processing engine
Proceedings of the 2008 ACM SIGMOD international conference on Management of data
Amdahl's Law in the Multicore Era
Computer
Analytical Modeling of Pipeline Parallelism
PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
IEC 61131-3: Programming Industrial Automation Systems Concepts and Programming Languages, Requirements for Programming Systems, Decision-Making Aids
Disciplined heterogeneous modeling
MODELS'10 Proceedings of the 13th international conference on Model driven engineering languages and systems: Part II
Software Pipelining for Stream Programs on Resource Constrained Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
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This paper presents a novel pipelining technique designed specifically to improve the execution of cyclic control systems and applications in terms of scan cycle time reduction and/or execution of additional workload. Based on the observation that cyclic control systems are tightly coupled with physical processes and that state information (e.g. on/off signals, temperature, pressure) is the most critical data in an application, we present new execution schemes that overlap the execution of multiple cycles in multi-core processors over time. Using an edge detection application benchmark and a software real-time PLC (Programmable Logic Controller) implementation on a quad-core processor, we validate our pipelining method and show the performance scalability of the various schemes. Additionally, we analyze the resilience of our pipelining approach to time delays and propose a speculative execution method to deal with data dependency violations.