ACM SIGOPS Operating Systems Review
Priority Inheritance Protocols: An Approach to Real-Time Synchronization
IEEE Transactions on Computers
Predictable Interrupt Management for Real Time Kernels over conventional PC Hardware
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Predictable Interrupt Scheduling with Low Overhead for Real-Time Kernels
RTCSA '06 Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Process-Aware Interrupt Scheduling and Accounting
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
Architectural Characterization of Processor Affinity in Network Processing
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Efficient operating system scheduling for performance-asymmetric multi-core architectures
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
ACM Transactions on Embedded Computing Systems (TECS)
Corey: an operating system for many cores
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
Synchronization mechanisms on modern multi-core architectures
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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The demands of modern embedded systems are hastening the adoption of multicore SoCs. Although multicore SoCs can be conceptually viewed as distributed systems, the resources on multicore SoCs including interrupts and scheduling are mostly, if not all, managed by the operating systems on general purpose CPU on SoC in a centralized manner. This approach leads to heavy overhead on the general purpose CPU and does not scale up. This paper presents the design and implementation of a microkernel for multi-core DSP SoCs, named nμKernel, to support real-time scheduling, load sharing among DSP cores, nested priority interrupts, and predictable interrupt latency jitter. The kernel takes advantage of both the shared memory architecture on multicore DSP SoCs and pipeline real-time scheduling to support load sharing. A server-base algorithm is designed for overrun control and to reduce load sharing overhead. The developed hybrid interrupt handling framework adopts on-demand interrupt thread mechanism to reduce interrupt handling overhead and support nested priority interrupts. The experiments show that the kernel can significantly enhance application performance with least management overhead. The frame rate of a secure image display application speeds up for six times: from 2.2 frames per second to 19 frames per second while workload are shared among DSP cores. The developed interrupt handling framework shortens the interrupted latency for up to 90%, compared to two-level interrupt handling mechanism and limits the range of interrupt latency to no more than 5%.