Boosting instruction set simulator performance with parallel block optimisation and replacement

  • Authors:

  • Brad Alexander;Sean Donnellan;Andrew Jeffries;Travis Olds;Nicholas Sizer

  • Affiliations:

  • University of Adelaide, Adelaide;Ultra Electronics Avalon Systems, Mawson Lakes, South Australia;Ultra Electronics Avalon Systems, Mawson Lakes, South Australia;Australian Semiconductor Technology Company, Adelaide, South Australia;Australian Semiconductor Technology Company, Adelaide, South Australia

  • Venue:
  • ACSC '12 Proceedings of the Thirty-fifth Australasian Computer Science Conference - Volume 122
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

Time-to-market is a critical factor in the commercial success of new consumer devices. To minimise delays, system developers and third party software vendors must be able to test their applications before the hardware platform becomes available. Instruction Set Simulators (ISS's) underpin this early development by emulating new platforms on ordinary desktop machines. As target platforms become faster the performance demands on ISS's become greater. A key challenge is to leverage available simulator technology to produce, at low cost, incremental performance gains needed to keep up with these demands. In this work we use a very simple strategy: in-place-block-replacement to produce improvements in the performance of the popular QEMU functional simulator. The replacement blocks are generated at runtime using the LLVM JIT running on spare processor cores. This strategy provides a very lightweight way to incrementally build an alternate code generator within an existing ISS framework without incurring a substantial runtime cost. We show the approach is effective in reducing the runtimes of the QEMU user-space emulator on a number of SPECint 2006 benchmarks.