LECSIM: a levelized event driven compiled logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
A Robust Automated Scan Pattern Mismatch Debugger
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
SOCRATES: a highly efficient automatic test pattern generation system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose an implication graph based sequential logic simulator for debugging scan pattern failures encountered during First Silicon. A novel Debug Implication Graph (DIG) is constructed during logic simulation of the failing scan pattern. An efficient node traversal mechanism across time frames, in the DIG, is used to perform the root-cause analysis for the failing scan-cells. We have developed an Interactive Pattern Debug environment (IDE), viz. scan pattern debugger, around the logic simulator to systematically analyze and root-cause the failures. We integrated the proposed technique into the scan ATPG flow for industrial microprocessor designs. We were able to resolve the First Silicon logical pattern failures within hours, which would have otherwise taken a few days of manual effort.