Improving NAND endurance by dynamic program and erase scaling

Authors:
Jaeyong Jeong;Sangwook Shane Hahn;Sungjin Lee;Jihong Kim
Affiliations:
Department of Computer Science and Engineering, Seoul National University, Korea;Department of Computer Science and Engineering, Seoul National University, Korea;Department of Computer Science and Engineering, Seoul National University, Korea;Department of Computer Science and Engineering, Seoul National University, Korea
Venue:
HotStorage'13 Proceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems
Year:
2013

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Abstract

We propose a new approach, called dynamic program and erase scaling (DPES), for improving the endurance of NAND flash memory. The DPES approach is based on our key finding that the NAND endurance is dependent on the erase voltage as well as the number of P/E cycles. Since the NAND endurance has a near-linear dependence on the erase voltage, lowering the erase voltage is an effective way of improving the NAND endurance. By modifying NAND chips to support multiple write modes with different erase voltages, DPES enables a flash software to exploit the new tradeoff between the NAND endurance and write speed. In this paper, we present a novel NAND endurance model which accurately captures the tradeoff relationship between the endurance and write speed under dynamic program and erase scaling. Based on our NAND endurancemodel, we have implemented the first DPES-aware FTL, called autoFTL, which improves the NAND endurance with a negligible degradation in the overall write throughput. Our experimental results using various I/O traces show that autoFTL can improve the maximum number of P/E cycles by 45% over an existing DPES-unaware FTL with less than 0.2% decrease in the overall write throughput.