Efficient identification of hot data for flash memory storage systems
ACM Transactions on Storage (TOS)
On efficient wear leveling for large-scale flash-memory storage systems
Proceedings of the 2007 ACM symposium on Applied computing
Write off-loading: practical power management for enterprise storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
How i learned to stop worrying and love flash endurance
HotStorage'10 Proceedings of the 2nd USENIX conference on Hot topics in storage and file systems
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
Exploiting heat-accelerated flash memory wear-out recovery to enable self-healing SSDs
HotStorage'11 Proceedings of the 3rd USENIX conference on Hot topics in storage and file systems
Optimizing NAND flash-based SSDs via retention relaxation
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Lifetime management of flash-based SSDs using recovery-aware dynamic throttling
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Improving NAND endurance by dynamic program and erase scaling
HotStorage'13 Proceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems
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The cost-per-bit of NAND flash memory has been continuously improved by semiconductor process scaling and multi-leveling technologies (e.g., a 10 nm-node TLC device). However, the decreasing lifetime of NAND flash memory as a side effect of recent advanced technologies is regarded as a main barrier for a wide adoption of NAND flash-based storage systems. In this paper, we propose a new system-level approach, called dynamic program and erase scaling (DPES), for improving the lifetime (particularly, endurance) of NAND flash memory. The DPES approach is based on our key observation that changing the erase voltage as well as the erase time significantly affects the NAND endurance. By slowly erasing a NAND blockwith a lower erase voltage, we can improve the NAND endurance very effectively. By modifying NAND chips to support multiple write and erase modes with different operation voltages and times, DPES enables a flash software to exploit the new tradeoff relationships between the NAND endurance and erase voltage/ speed under dynamic program and erase scaling. We have implemented the first DPES-aware FTL, called autoFTL, which improves the NAND endurance with a negligible degradation in the overall write throughput. Our experimental results using various I/O traces show that autoFTL can improve the maximum number of P/E cycles by 61.2% over an existing DPES-unaware FTL with less than 2.2% decrease in the overall write throughput.