Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
New continuous-time multibit sigma-delta modulators with low sensitivity to clock jitter
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Analysis and design of voltage-controlled oscillator based analog-to-digital converter
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A brief introduction to time-to-digital and digital-to-time converters
IEEE Transactions on Circuits and Systems II: Express Briefs
Analysis and design of an ultralow-power CMOS relaxation oscillator
IEEE Transactions on Circuits and Systems Part I: Regular Papers
| Hi-index | 0.00 |
A new Frequency-to-Digital (F2D) converter based on a Phase-Locked Loop (PLL) is presented in this paper where the square wave at the output of a Voltage Controlled Oscillator (which is also the PLL output) is sampled and fed back to one of the Phase-Frequency Detector inputs. This sampled output is digitally processed and the information carried in its frequency is converted to a digital signal by means of a digital differentiator. Theoretical analyses and system-level simulations show that the errors produced by the sampling are shaped by a high-order transfer function in the same way as quantization errors are shaped in a Sigma-Delta Modulator. In addition, transistor-level simulations show a low sensitivity to non-linear circuit errors. The proposed F2D converter is suitable for integration in modern nanometer CMOS technologies, and can be used as an FM demodulator.