An SIMD programmable vision chip with high-speed focal plane image processing
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
APRON: a cellular processor array simulation and hardware design tool
EURASIP Journal on Advances in Signal Processing - CNN technology for spatiotemporal signal processing
An Ultra-Low-Power Contrast-Based Integrated Camera Node and its Application as a People Counter
AVSS '10 Proceedings of the 2010 7th IEEE International Conference on Advanced Video and Signal Based Surveillance
Low power high-performance smart camera system based on SCAMP vision sensor
Journal of Systems Architecture: the EUROMICRO Journal
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A prototype vision chip has been designed that incorporates a 20 脳 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.