A 0.1---4 GHz SDR receiver with reconfigurable 10---100 MHz signal bandwidth in 65 nm CMOS

Authors:
Xinwang Zhang;Baoyong Chi;Meng Cao;Ling Fu;Zhaokang Xia;Yun Yin;Hongxing Feng;Xing Zhang;Patrick Chiang;Zhihua Wang
Affiliations:
Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084;School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, USA 97331-5501;Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, China 100084
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2013

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Abstract

A 0.1---4 GHz software-defined radio (SDR) receiver with reconfigurable 10---100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm2. The receiver achieves S11 input matching below 驴10 dB and a NF of 3---8 dB across the 0.1---4 GHz range, and a maximum gain of 82---92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.