Bias and geometry optimization of FinFET for RF stability performance

Authors:
K. Sivasankaran;P. S. Mallick
Affiliations:
School of Electrical Engineering, VIT University, Vellore, India;School of Electrical Engineering, VIT University, Vellore, India
Venue:
Journal of Computational Electronics
Year:
2014

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Abstract

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (fk) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.