Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Java intermediate bytecodes: ACM SIGPLAN workshop on intermediate representations (IR'95)
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Java for C/C++ programmers
Core Java
Design, implementation, and evaluation of optimizations in a just-in-time compiler
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Java annotation-aware just-in-time (AJIT) complilation system
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Using complete system simulation to characterize SPECjvm98 benchmarks
Proceedings of the 14th international conference on Supercomputing
A single intermediate language that supports multiple implementations of exceptions
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Java Runtime Systems: Characterization and Architectural Implications
IEEE Transactions on Computers
Techniques for obtaining high performance in Java programs
ACM Computing Surveys (CSUR)
Characterizing operating system activity in SPECjvm98 Benchmarks
Workload characterization of emerging computer applications
Exploiting Java instruction/thread level parallelism with horizontal multithreading
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Compiling scheme to JVM bytecode:: a performance study
Proceedings of the seventh ACM SIGPLAN international conference on Functional programming
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Embedded processor design challenges
The simplest heuristics may be the best in Java JIT compilers
ACM SIGPLAN Notices
How java programs interact with virtual machines at the microarchitectural level
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A dynamic compiler for embedded Java virtual machines
Proceedings of the 3rd international symposium on Principles and practice of programming in Java
Proceedings of the 3rd international symposium on Principles and practice of programming in Java
A selective dynamic compiler for embedded Java virtual machines targeting ARM processors
Science of Computer Programming - Special issue: Principles and practices of programming in Java (PPPJ 2004)
Transient variable caching in Java’s stack-based intermediate representation
Scientific Programming
ICHIT'06 Proceedings of the 1st international conference on Advances in hybrid information technology
Formalisation and implementation of an algorithm for bytecode verification of @NonNull types
Science of Computer Programming
Target code generation sing the code expansion technique for java bytecode
PDCAT'04 Proceedings of the 5th international conference on Parallel and Distributed Computing: applications and Technologies
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The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in Java bytecode are expected to run without modification on multiple platforms. These first generation run-time environments rely on an interpreter to bridge the gap between the bytecode instructions and the native hardware. This interpreter approach is sufficient for specialized applications such as Internet browsers where application performance is often limited by network delays rather than processor speed. It is, however, not sufficient for executing general applications distributed in Java bytecode. This paper presents our initial prototyping experience with Caffeine, an optimizing translator from Java bytecode to native machine code. We discuss the major technical issues involved in stack to register mapping, run-time memory structure mapping, and exception handlers. Encouraging initial results based on our X86 port are presented.