Computer
HPSm, a high performance restricted data flow architecture having minimal functionality
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)
Exploiting parallel microprocessor microarchitectures with a compiler code generator
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
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HPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurrency in the microarchitecture. Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both control intensive and floating point intensive benchmarks. For both types of benchmarks, we show that the HPSm microarchitecture achieves significant speedup over the RISC/SPUR microarchitecture implemented with the same fabrication technology.