Programming perl
How to write Awk and Perl scripts to enable your EDA tools to work together
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A Methodology for Hardware Architecture Trade-off at Different Levels of Abstraction
EDTC '97 Proceedings of the 1997 European conference on Design and Test
| Hi-index | 0.00 |
A methodology for architecture exploration of look-up tablebased decoders is presented. For the degree of parallel processinga trade-off can be made by exploring system leveland register transfer level models. Executable specifications(pure functional software models, VHDL behavior models)are used to analyze the performance of different architectures.Hardware cost (area) and feasibility (timing) aredetermined by synthesis of RTL models. These models aregenerated directly out of the specification to avoid errorsdue to manual transformations and to reduce overall designtime. Generator-based reuse modeling and hardware costestimation is demonstrated using a decoder for MPEG variablelength codes (VLC).