Programming perl
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reuse scenario for the VHDL-based hardware design flow
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Architectural exploration for datapaths with memory hierarchy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A parallel/serial trade-off methodology for look-up table based decoders
DAC '97 Proceedings of the 34th annual Design Automation Conference
Si-Emulation: System Verification Using Simulation and Emulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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In this paper a method of architecture exploration and selection is presented. Compared with other approaches, no special tools or modeling languages are needed - instead the models and tools of the ASIC design flow are used. The architecture trade-off process is performed iteratively, and considers information from different levels of abstraction in parallel. At system level, software and behavioral models, which are part of executable specifications are examined to get the necessary top-down information (performance). Bottom-up information (hardware costs) for irregular hardware structures is obtained by generating, analyzing and synthesizing VHDL code at RT-Level. For regular structures, formulas or tables can be used to estimate area and timing. The proposed approach was successfully performed for parts of a multimedia design, where an executable specification (in 'C') was available together with the standard.