Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Parallel computing: theory and comparisons
Parallel computing: theory and comparisons
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
IEEE Transactions on Computers
Implementing atomic sequences on uniprocessors using rollforward
Software—Practice & Experience
Heterogeneous built-in resiliency of application specific programmable processors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Computer Architecture; Case Studies
Computer Architecture; Case Studies
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Hi-index | 0.00 |
Task preemption is a critical enabling mechanism in multi-task VLSI systems. On preemption, data in the register files must be preserved in order for the task to be resumed. This entails extra memory to preserve the context and additional clock cycles to save and restore the context. In this paper, we present techniques and algorithms to incorporate micro-preemption constraints during multi-task VLSI system synthesis. Specifically, we have developed: (i) Algorithms to insert and refine preemption points in scheduled task graphs subject to preemption latency constraints. (ii) Techniques to minimize the context switch overhead by considering the dedicated registers required to save the state of a task on preemption and the shared registers required to save the remaining values in the tasks. (iii) A controller based scheme to preclude preemption related performance degradation. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on real examples.