Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
Lazy-expansion symbolic expression approximation in SYNAP
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computer Methods for Circuit Analysis and Design
Computer Methods for Circuit Analysis and Design
Symbolic Analysis for Automated Design of Analog Integrated Circuits
Symbolic Analysis for Automated Design of Analog Integrated Circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
MAELSTROM: efficient simulation-based synthesis for custom analog cells
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic circuit-noise analysis and modeling with determinant decision diagrams
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Efficient DDD-based symbolic analysis of large linear analog circuits
Proceedings of the 38th annual Design Automation Conference
Analog Integrated Circuits and Signal Processing
Journal of Global Optimization
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Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction and DDD-based symbolic analysis can be performed in time complexity proportional to the number of DDD vertices. We described a vertex ordering heuristic, and showed that the number of DDD vertices can be quite small --- usually orders-of-magnitude less than the number of product terms. The algorithm has been implemented. An order-of-magnitude improvement in both CPU time and memory usages over existing symbolic analyzers ISAAC and Maple-V has been observed for large analog circuits.