Simulated annealing for VLSI design
Simulated annealing for VLSI design
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Linear decomposition algorithm for VLSI design applications
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New spectral linear placement and clustering approach
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The placement problem as viewed from the physics of classical mechanics
DAC '75 Proceedings of the 12th Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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This paper addresses a placement method good for module generation. Conventional partitioning based method can not guarantee the best quality in consecutive partitioning, even if it can find a sequence of the minimum partitioning of a circuit into two subcircuits. Also, when size of cells varies very much, which is often seen in module generation as leaf cells, it is sometimes too strong constraint for them to get the minimum partitioning under ``partitioning into two similar size of subcircuits''. On the other hand, although conventional Simulated Annealing (SA) based method gives a better result, it requires extremely long computation time, since they do not employ any divide and conquer technique. It is the purpose of this paper to propose an algorithm which is based on SA method and employs the divide and conquer technique so that it gives better quality than partitioning based method and also it gives drastically faster computation time than SA method. As the first step, we applied this idea to the linear placement. Our algorithm is based on sorting inside subgroups, and this subgroup generation is done by plural cut-lines with a constant pitch. This constant pitch will be decreased from sufficiently large value to small value gradually, and this decreasing schedule is similar to the cooling schedule of SA method. And also, since there is a variation of offset in applying cut-lines even with the same pitch value, we randomly select one of them like SA method chooses a pair of components to be switched at random. Sorting inside subgroups is only a rearrangement depending on the connection between subgroups and is very fast. It is found that the total wiring length is improved about 10% compared to that of spectral method which was recognized to be the best (SLPC2). Also, computation time was dramatically reduced over the SA method.