A modular systolic architecture for image convolutions

Authors:
K. Doshi;P. Varman
Affiliations:
Department of Electrical and Computer Engineering, Rice University, Houston, TX;Department of Electrical and Computer Engineering, Rice University, Houston, TX
Venue:
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Year:
1987

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Abstract

This paper describes a modular, systolic design for two-dimensional convolution which is a frequent and computationally intensive operation in low-level image processing. The design consists of a one-dimensional array of homogeneous cells, each with a fixed amount of storage. The paper also presents schema by which the design consisting of a limited number of cells can be used to implement convolutions of varying kernel sizes, with optimal throughput. The design is simple and hence a good candidate for VLSI integration. Its one-dimensional organization and unidirectional data flow characteristics result in good fault-tolerance for the array.