The architecture of a programmable systolic chip
Advances in VLSI and Computer Systems
A Method for Obtaining Skeletons Using a Quasi-Euclidean Distance
Journal of the ACM (JACM)
Use of the Hough transformation to detect lines and curves in pictures
Communications of the ACM
Digital Picture Processing
The cytocomputer: A practical pipelined image processor
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
A modular systolic architecture for image convolutions
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Computing the Hough Transform on a Scan Line Array Processor (Image Processing)
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel Architectures and Algorithms for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
Efficient Image Processing Algorithms on the Scan Line Array Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence
Finding connected components on a scan line array processor
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Neural computing on a one dimensional SIMD array
IJCAI'89 Proceedings of the 11th international joint conference on Artificial intelligence - Volume 1
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This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.