Processor design for portable systems
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power DSP's for wireless communications (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low-power embedded DSP core for communication systems
EURASIP Journal on Applied Signal Processing
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This paper describes the architecture and the performance of a newprogrammable 16-bit Digital Signal Processor (DSP) engine. It is developedspecifically for next generation wireless digital systems and speechapplications. Besides providing a basic instruction set, similar to currentday 16-bit DSP‘s, it contains distinctive architectural features and uniqueinstructions, which make the engine highly efficient for compute-intensivetasks such as vector quantization and Viterbi operations. The datapathcontains two Multiply-Accumulate units and one ALU. The external memorybandwidth is kept to two data busses and two corresponding address busses.Still, the internal bus network is designed such that all three units areoperating in parallel. This parallelism is reflected in the performancebenchmarks. For example, an FIR filter of N taps will take N/2 instructioncycles compared to N for a general purpose 16-bit DSP, and it will requireonly half the number of memory accesses of a general purpose DSP. Thisefficiency is reflected in the very low MIPS requirement to implementcellular standards.