A Low Power DSP Engine for Wireless Communications
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
The mobile phone meets the Internet
IEEE Spectrum
DSP-based architectures for mobile communications: past, present and future
IEEE Communications Magazine
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
Reconfigurable interconnect for next generation systems
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An energy saving strategy based on adaptive loop parallelization
Proceedings of the 39th annual Design Automation Conference
Challenges and opportunities in broadband and wireless communication designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Skiing the embedded systems mountain
ACM Transactions on Embedded Computing Systems (TECS)
Low-power embedded DSP core for communication systems
EURASIP Journal on Applied Signal Processing
Intra-vector SIMD instructions for core specialization
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Early exploration for platform architecture instantiation with multi-mode application partitioning
Proceedings of the 50th Annual Design Automation Conference
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Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSPs). In this tutorial, an overview will be given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors. Please note that the authors do not endorse the processors used in this tutorial. These processors are used to illustrate how different solutions are proposed for the same problem.