IEEE Transactions on Computers
Design of self-testing checkers for m-out-of-n codes using parallel counters
On-line testing for VLSI
Efficient Modular Design of TSC Checkers for M-out-of-2M-Codes
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient Totally Self-Checking Checkers for a Class of Borden Codes
IEEE Transactions on Computers
Concurrent Error Detection in Wavelet Lifting Transforms
IEEE Transactions on Computers
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We present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for $m$-out-of-$n$ code, where $m \geq 3$, $2m+1 \leq n \leq 4m$. The checker is composed of four special adders which sum the 1s in the primary inputs added by appropriate constants, two ripple carry adders which sum the outputs of the biased-adders, and a $k$-variable two-rail code checker tree which compares the outputs of the two ripple carry adders, where $k=\lfloor \log_2 (n-m)+ 1 \rfloor$. All the modules are composed of 2-input gates and inverters. Compared with previous nonmodular methods, our TSC checker has a lower hardware and time complexity: Our method reduces the hardware complexity and circuit delay of the checker from $O(n^2)$ to $O(n)$ and from $O(n)$ to $O(\log_2 n)$, respectively. Compared with recent modular methods, our TSC checker has about the same hardware and time complexity, but is applicable to a much broader range of $n$. In summary, our method is superior to existing methods for the considered range of $n$. In addition, our TSC checker can easily be tested (the test set size of our TSC checker is relatively small) and implemented in VLSI for its modular structure.