The K2 parallel processor: architecture and hardware implementation

Authors:
Marco Annaratone;Marco Fillo;Kiyoshi Nakabayashi;Marc Viredaz
Affiliations:
Integrated Systems Laboratory, Swiss Federal Institute of Technology, Gloriastrasse 35, 8092 Zurich, Switzerland;Integrated Systems Laboratory, Swiss Federal Institute of Technology, Gloriastrasse 35, 8092 Zurich, Switzerland;NTT Communications and Information Processing Laboratories, Tokyo 180, Japan;Integrated Systems Laboratory, Swiss Federal Institute of Technology, Gloriastrasse 35, 8092 Zurich, Switzerland
Venue:
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Year:
1990

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Abstract

K2 is a distributed-memory parallel processor designed to support a multi-user, multi-tasking, time-sharing operating system and an automatically parallelizing FORTRAN compiler. This paper presents the architecture and the hardware implementation of K2, and focuses on the architectural features required by the operating system and the compiler. A prototype machine with 24 processors is currently being developed.