The iPSC/2 direct-connect communications technology
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
iPSC/2 system: a second generation hypercube
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Application performance improvement on the iPSC/2 computer
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
A message passing coprocessor for distributed memory multicomputers
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Parallel Quicksort in hypercubes
SAC '92 Proceedings of the 1992 ACM/SIGAPP symposium on Applied computing: technological challenges of the 1990's
A hardware-based performance monitor for the Intel iPSC/2 hypercube
ICS '90 Proceedings of the 4th international conference on Supercomputing
The K2 parallel processor: architecture and hardware implementation
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
Design Considerations for Shared Memory Multiprocessor Message Systems
IEEE Transactions on Parallel and Distributed Systems
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Feedback from users of the first generation ISP system plus the development and availability of new VLSI based technologies drove the design of the iPSC/2 node. The new node design was broadly governed by the following goals:Provide true 32-bit node architecture and performance.Match the communication performance to the computational performance.Increase on board memory capacity by using new RAM technology.Employ a modular functional elements to easily incorporate future technology.Allow plug compatibility with existing iPSC systems, including interface to co-processors.Ensure software compatibility for existing iPSC applications.This paper describes how the iPSC/2 node achieved these goals by leveraging Intel's VLSI expertise and products, surface mount, CMOS and gate array technologies, and small daughter boards to implement modular subsystems.