A message passing coprocessor for distributed memory multicomputers

Authors:
Jiun-Ming Hsu;Prithviraj Banerjee
Affiliations:
Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois;Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois
Venue:
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Year:
1990

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Abstract

This paper presents the architecture, methodology and performance evaluation of a message passing coprocessor (MPC) which can accelerate message communication in a distributed memory multicomputer. The MPC is a microprogrammable processor which off-loads the CPU of the burden of communication and speeds up the software processing by directly executing message passing instructions in microcode. It supports process scheduling, message buffer management, and fast buffer copying. The most unique feature of the MPC is that it performs software caching for expected message destinations and buffers. The MPC works closely with a virtual channel router [1] which is a smart routing controller and supports virtual channels and cached circuits. The software and hardware overhead of communication can be reduced significantly by these two processors. The performance is confirmed by trace driven simulation.