Communications of the ACM - Special section on computer architecture
The C++ programming language
Hyperswitch network for the hypercube computer
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Mark IIIfp hypercube concurrent processor architecture
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
A message passing coprocessor for distributed memory multicomputers
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
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The performance of a message-passing multiple instruction multiple data (MIMD) concurrent computer depends in large part on the communication processing overhead. A high-speed communication architecture is proposed for a hypercube-type supercomputer to attain the specific goals of message-driven processing. These goals include: direct hardware execution of messages, queueing of messages (using various paradigms), adaptive message routing, and special local registers for fast context switching. A hyperswitch network capable of high-speed switching is used to perform message routing. Available communication paths are pruned by the routing algorithm in response to congestion within the network to evaluate the best-first available path between any two nodes. Simulation results show that this architecture reduces message reception latency by two to three orders of magnitude when compared to commercial hypercube systems. This communication architecture extends the application of parallel systems to supercomputer problems that place heavy demand on the communication network for high bandwidth, low latency, and non-local communication. Detailed simulation studies for the proposed communication architecture are presented.