Mark IIIfp hypercube concurrent processor architecture

Authors:
J. Tuazon;J. Peterson;M. Pniel
Affiliations:
Jet Propulsion Laboratory, Pasadena, CA and Professor of Electrical Engineering, California State University, Fullerton, CA;Jet Propulsion Laboratory, Pasadena, CA and Member of the Technical Staff, Concurrent Processor Systems Group, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA;Jet Propulsion Laboratory, Pasadena, CA and Member of the Technical Staff, Concurrent Processor Systems Group, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA
Venue:
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Year:
1988

Citing 1
Cited 7

The cosmic cube

Communications of the ACM - Special section on computer architecture

A high-speed message-driven communication architecture

ICS '88 Proceedings of the 2nd international conference on Supercomputing
Parallel programming in comfort

C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
A message passing coprocessor for distributed memory multicomputers

Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Low-latency message communication support for the AP1000

ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Processor scheduling on multiprogrammed, distributed memory parallel computers

SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Performance measurement and trace driven simulation of parallel CAD and numeric applications on a hypercube multicomputer

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer

IEEE Transactions on Parallel and Distributed Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Mark lllfp Hypercube is a new generation of hypercube concurrent processor system developed at JPL/Caltech, with peak performance of 5 Mips, 14 Mflops per node, and a peak communication rate of 6 Mbytes per second. Each node utilizes two Motorola MC68020 microprocessors, an MC68882 scalar floating- point coprocessor, and a Weitek 8000 floating-point chip set. One of the MC68020 processors serves as the application and computational processor, the other is dedicated to communication. The three processors are interconnected through a common system bus and share 4 Mbytes of dynamic memory. Each processor has his own fast local memory, which increases parallelism, minimizes shared memory referencing, reduces memory contentions and improves system performance.