Interprocessor communication speed and performance in distributed-memory parallel processors

  • Authors:
  • M. Annaratone;C. Pommerell;R. Rühl

  • Affiliations:
  • Integrated Systems Labomtory, Swiss Federal Institute of Technology, 8092 Zurich, Switzerland;Integrated Systems Labomtory, Swiss Federal Institute of Technology, 8092 Zurich, Switzerland;Integrated Systems Labomtory, Swiss Federal Institute of Technology, 8092 Zurich, Switzerland

  • Venue:
  • ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
  • Year:
  • 1989

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Abstract

We have simulated several numerical and non-numerical algorithms on five distributed-memory parallel processors (DMPPs). All five DMPPs have the same topology (a torus), and the same number of nodes. The architectures differ only in the communication speed between neighboring nodes, while the computation unit is kept unchanged. The goal of the paper is to quantify the effect that interprocessor communication speed and synchronization overhead have on the performance of the DMPPs. After introducing the rationale for this study and reviewing related work, we present and discuss the results of the simulations.