Average case analysis of greedy routing algorithms on arrays
SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Architectural requirements of parallel scientific applications with explicit communication
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
A Flexible Bit-Pattern Associative Router for Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Strategic directions in networks and telecommunications
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Executing tree routing algorithms on a high-performance pattern associative router
Journal of Systems Architecture: the EUROMICRO Journal
A VLSI High-Performance Encoder with Priority Lookahead
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Valid clock frequencies and their computation in wavepipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time and power. The design approach considered in this paper allows the propagation of data from stage to stage to occur without the use of intermediate latches. Control signals are used to ensure that intermixing of data waves does not occur. The results of the study show that wave-pipelining helps to reduce the clock period.