A Hierarchical Block-Floating-Point Arithmetic

Authors:
Shiro Kobayashi;Gerhard P. Fettweis
Affiliations:
Mobile Communications Systems, Dresden University of Technology, 01026 Dresden, Germany;Mobile Communications Systems, Dresden University of Technology, 01026 Dresden, Germany
Venue:
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Year:
2000

Citing 5
Cited 2

Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
DSP Processor Fundamentals: Architectures and Features

DSP Processor Fundamentals: Architectures and Features
Implementation Options for Block Floating Point Digital Filters

ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97)-Volume 3 - Volume 3
A new approach for block-floating-point arithmetic

ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Roundoff errors in block-floating-point systems

IEEE Transactions on Signal Processing

Embedded DSP Processor Design: Application Specific Instruction Set Processors

Embedded DSP Processor Design: Application Specific Instruction Set Processors
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation

Proceedings of the great lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

In order to give an answer to a question of the arithmeticin future DSP architectures for mobile communication applications,the signal processing quality of different arithmetic representationshas been studied. Based on the result, a new approach forimplementing block-floating-point arithmetic is proposed. Thisapproach intends to preserve the least-significant-bits (LSBs) toimprove signal processing quality. The preservation of LSBs isautomatically and perfectly done by hardware. Serveral simulationresults show that the proposed block-floating-point implementationprovides improved SNRs over conventional block-floating-pointimplementations. For the same number of bits in the memory for eachrepresentation, the SNRs better than floating-point are alsoobserved. For multiple datapath DSPs, this implementation alsorequires significantly less hardware complexity thanfloating-point.