MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A Hierarchical Block-Floating-Point Arithmetic
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
FRIDGE: a fixed-point design and simulation environment
Proceedings of the conference on Design, automation and test in Europe
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A compiled accelerator for biological cell signaling simulations
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Automated Floating-Point to Fixed-Point Conversion with the Fixify Environment
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Hardware/software partitioning of software binaries: a case study of H.264 decode
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Accuracy constraint determination in fixed-point system design
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Roundoff errors in block-floating-point systems
IEEE Transactions on Signal Processing
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During the early design phases of software development, many developers use floating point data types and libraries but often convert these applications into fixed point representations in later design phases - a time consuming process often requiring significant designer effort. While various approaches have been proposed to automate the floating to fixed point conversion process, these approaches are mainly targeted at creating optimized software implementations and do not directly support partitioning floating point implementation to hardware. We present an approach to optimize the number of bits required for a dynamically adaptable fixed-point representation using SNR analysis methods targeting computationally intensive floating-point kernels. We present a hardware/software partitioning methodology that leverages this SNR analysis to partition application kernels to custom hardware coprocessors implemented within a field-programmable gate array. Using several case study applications, we highlight the performance benefits and area requirements of the resulting hardware implementations.